View CY7C68000-48BAC_1039066.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

tx2 ? usb 2.0 utmi transceiver cy7c68000 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-08016 rev. *b revised novermber 15, 2002 cy7c68000 tx2 ? usb 2.0 utmi transceiver
cy7c68000 document #: 38-08016 rev. *b page 2 of 14 table of contents 1.0 ez-usb tx2 features ....................................................................................................... ......... 3 2.0 applications .............................................................................................................. ................. 4 3.0 functional overview ....................................................................................................... ....... 4 3.1 usb signaling speed ....................................................................................................... .............. 4 3.2 transceiver clock frequency ............................................................................................... ......... 4 3.3 buses ..................................................................................................................... .......................... 4 3.4 reset pin ................................................................................................................. ........................ 4 3.5 line state ................................................................................................................ ......................... 4 3.6 full-speed vs. high-speed select .......................................................................................... ........ 4 3.7 operational modes ......................................................................................................... ................ 4 4.0 dplus/dminus impedance termination .............................................................................. 5 5.0 pin assignments ........................................................................................................... ............. 5 5.1 cy7c68000 pin descriptions ................................................................................................ ......... 6 6.0 absolute maximum ratings ................................................................................................ 10 7.0 operating conditions ...................................................................................................... ..... 10 8.0 dc characteristics ........................................................................................................ ....... 10 8.1 usb 2.0 transceiver ....................................................................................................... .............. 10 9.0 ac electrical characteristics ....................................................................................... 11 9.1 usb 2.0 transceiver ....................................................................................................... .............. 11 9.2 timing diagram ............................................................................................................ ................. 11 9.2.1 hs/fs interface timing?60 mhz ......................................................................................... .............. 11 9.2.2 hs/fs interface timing?30 mhz .......................................................................................... .............. 11 10.0 ordering information ..................................................................................................... ... 12 11.0 package diagrams ......................................................................................................... ...... 12 list of figures figure 1-1. block diagram ...................................................................................................... .............. 3 figure 5-1. cy7c68000 48-pin fbga pin assignment ....................................................................... 5 figure 5-2. cy7c68000 56-pin ssop pin assignment ....................................................................... 6 figure 9-1. 60-mhz interface timing constraints ............................................................................. 11 figure 9-2. 30-mhz timing interface timing constraints ................................................................ 11 figure 11-1. 56-lead shrunk small outline package o56 ................................................................ 12 figure 11-2. 48-pin fine pitch ball grid array (7 x 7 x 1.2 mm) ba48a .......................................... 13 list of tables table 5-1. pin descriptions .................................................................................................................. 6 table 8-1. dc characteristics ............................................................................................................ 10 table 9-1. 60-mhz interface timing constraints parameters ........................................................ 11 table 9-2. 30 mhz timing interface timing constraints parameters ............................................ 11 table 10-1. ordering information ...................................................................................................... 12
cy7c68000 document #: 38-08016 rev. *b page 3 of 14 1.0 ez-usb ? tx2 ? features the cypress ez-usb ? tx2 ? is a universal serial bus (usb) specification revision 2.0 transceiver, serial/deserializer, to a parallel interface of either 16 bits at 30 mhz or eight bits at 60 mhz. the tx2 provides a high-speed physical layer interface that oper ates at the maximum allowable usb 2.0 bandwidth. this allows the system designer to keep the complex high-speed analog usb components external to the digital asic which decreases development time and associated risk. a standard interface is provided that is usb 2.0-certified and is compliant with transceiver macrocell interface (utmi) specification version 1.05 dated 3/29/01 . two packages are defined for the family: 56-pin ssop and 48-pin fbga. the function block diagram is shown in figure 1-1 . utmi-compliant/usb-2.0-certified operates in both usb 2.0 high speed (hs), 480 mbits/second, and full speed (fs), 12 mbits/second serial-to-parallel and parallel-to-serial conversions 8-bit unidirectional, 8-bit bidirectional, or 16-bit bidirectional external data interface synchronous field and eop detection on receive packets synchronous field and eop generation on transmit packets data and clock recovery from the usb serial stream bit stuffing/unstuffing; bit stuff error detection staging register to manage data rate variation due to bit stuffing/unstuffing 16-bit 30-mhz, and 8-bit 60-mhz parallel interface ability to switch between fs and hs terminations and signaling supports detection of usb reset, suspend, and resume supports hs identification and detection as defined by the usb 2.0 specification supports transmission of resume signaling 3.3v operation two package options ? 48-pin fbga, and 56-pin ssop all required terminations, including 1.5-k ohm pull-up on dplus, are internal to chip supports usb 2.0 test modes. usb 2.0 xcvr traffic sync elasticity buffer fast digital rx digital rx digital tx fast digital tx full-speed rx full-speed tx high-speed tx high-speed rx bidi option also osc 20x pll pll_480 utmi clk xtalin/ out usb utmi rx ctl utmi tx ctl cy7c68000 utmi clk utmi rx data 8/16 utmi rx data 8/16 cy7c68000 figure 1-1. block diagram
cy7c68000 document #: 38-08016 rev. *b page 4 of 14 2.0 applications dsl modems ata interface memory card readers legacy conversion devices cameras scanners home pna wireless lan mp3 players networking. 3.0 functional overview 3.1 usb signaling speed tx2 operates at two of the rates defined in the usb specification 2.0, dated april 27, 2000: full speed, with a signaling bit rate of 12 mbps high speed, with a signaling bit rate of 480 mbps. tx2 does not support the low-speed (ls) signaling rate of 1.5 mbps. 3.2 transceiver clock frequency tx2 has an on-chip oscillator circuit that uses an external 24-mhz (100-ppm) crystal with the following characteristics: parallel resonant fundamental mode 500- w drive level 27 ? 33 pf (5% tolerance) load capacitors. an on-chip phase-locked loop (pll) multiplies the 24-mhz oscillator up to 30/60 mhz, as required by the transceiver parallel da ta bus. the default utmi interface clock (clk) frequency is determined by the databus16_8 pin. 3.3 buses the two packages allow for either 8- or 8/16-bit bidirectional data bus for data transfers to a controlling unit. the 48-pin package allows only 8-bit transfers while the 56-pin package adds an additional 8 bits to allow for a selection of 8 - or 16-bit transfers. 3.4 reset pin an input pin (reset) resets the chip. this pin has hysteresis and is active high according to the utmi specification. the inter nal pll stabilizes approximately 200 s after v cc has reached 3.3v. 3.5 line state the line state output pins linestate[1:0] are driven by combinational logic and may be toggling between the ? j ? and the ? k ? states. they are synchronized to the clk signal for a valid signal. on the clk edge the state of these lines reflect the state of the usb data lines. upon the clock edge the 0-bit of the linestate pins is the state of the dplus line and the one bit of lines tate is the dminus line. when synchronized, the set-up and hold timing of the linestate is identical to the parallel data bus. 3.6 full-speed vs. high-speed select the fs vs. hs is done through the use of both xcvrselect and the termselect input signals. the termselect signal enables the 1.5 k ohm pull-up on to the dplus pin. when termselect is driven low, a se0 is asserted on the usb providing the hs termination and generating the hs idle state on the bus. the xcvrselect signal is the control which selects either the fs trans - ceivers or the hs transceivers. by setting this pin to a ? 0 ? the hs transceivers are selected and by setting this bit to a ? 1 ? the fs transceivers are selected. 3.7 operational modes the operational modes are controlled by the opmode signals. the opmode signals are capable of inhibiting normal operation of the transceiver and evoking special test modes. these modes take effect immediately and take precedence over any pending data operations. the transmission data rate when in opmode depends on the state of the xcvrselect input.
cy7c68000 document #: 38-08016 rev. *b page 5 of 14 mode 0 allows the transceiver to operate with normal usb data decoding and encoding. mode 1 allows the transceiver logic to support a soft disconnect feature which three-states both the hs and fs transmitters, an d removes any termination from the usb, making it appear to an upstream port that the device has been disconnected from the bus. mode 2 disables bit stuff and nrzi encoding logic so 1s loaded from the data bus becomes js on the dplus / dminus lines and 0s become ks. 4.0 dplus/dminus impedance termination the cy7c68000 does not require external resistors for usb data line impedance termination or an external pull up resistor on the dplus line. these resistors are incorporated into the part. they are factory trimmed to meet the requirements of usb 2.0. incorporating these resistors also reduces the pin count on the part. 5.0 pin assignments the following pages illustrate the individual pin diagrams, plus a combination diagram showing which of the full set of signals are available in the 48- and 56-pin packages. the 48-pin package is the lowest-cost version and provides an 8-bit, 60-mhz interface. the 56-pin package is the full version, offering an 8-bit (60-mhz) or 16-bit (30-mhz) bus interface. the two signals required f or 16-bit operation are validh and databus16_8, and are present only in the 56-pin version. opmode[1:0] mode description 00 0 normal operation 01 1 non-driving 10 2 disable bit stuffing and nrzi encoding 11 3 reserved a1 a2 a3 a4 a5 a6 b1 b2 b3 b4 b5 b6 h1 h2 h3 h4 h5 h6 g1 g2 g3 g4 g5 g6 f1 f2 f3 f4 f5 f6 e1 e2 e3 e4 e5 e6 d1 d2 d3 d4 d5 d6 c1 c2 c3 c4 c5 c6 48-pin fbga figure 5-1. cy7c68000 48-pin fbga pin assignment agnd agnd clk gnd rxvalid opmode1 linestate1 linestate0 dminus gnd gnd gnd rxactive rxerror dplus reserved v cc v cc termselect xcvrselect opmode0 d7 d6 d5 d4 d3 d2 d1 d0 reserved reserved reserved reserved reserved reserved gnd v cc v cc v cc nc xtalout xtalin av cc av cc reset suspend txvalid txready
cy7c68000 document #: 38-08016 rev. *b page 6 of 14 5.1 cy7c68000 pin descriptions table 5-1. pin descriptions [1] 56 48 name type default description 11 b6 avcc power n/a analog v cc . this signal provides power to the analog section of the chip. 15 c6 avcc power n/a analog v cc . this signal provides power to the analog section of the chip. 14 a1 agnd power n/a analog ground . connect to ground with as short a path as possible. 18 b1 agnd power n/a analog ground . connect to ground with as short a path as possible. 16 a3 dplus i/o/z z usb dplus signal . connect to the usb dplus signal. 17 a2 dminus i/o/z z usb dminus signal . connect to the usb dminus signal. note: 1. unused inputs should not be left floating. tie either high or low as appropriate. outputs that are three-statable should only be pulled up or down to ensure signals at power-up and in standby. 56-pin ssop figure 5-2. cy7c68000 56-pin ssop pin assignment dplus 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 clk databus16_8 uni_bidi gnd txvalid v cc validh txready suspend reset avcc xtalout xtalin agnd avcc dminus agnd xcvrselect termselect opmode0 opmode1 gnd v cc linestate0 linestate1 gnd rxvalid d10 d0 d1 reserved d2 v cc d3 d4 gnd d5 reserved d6 d7 d8 d9 reserved d11 v cc d12 gnd d13 v cc d14 d15 reserved reserved rxerror rxactive
cy7c68000 document #: 38-08016 rev. *b page 7 of 14 56 h6 d0 i/o bidirectional data bus . this bidirectional bus is used as the entire data bus in the 8-bit mode or the least significant eight bits in the 16-bit mode. 55 g6 d1 i/o 53 h5 d2 i/o 51 g5 d3 i/o 50 h4 d4 i/o 48 g4 d5 i/o 46 h3 d6 i/o 45 g3 d7 i/o 44 ? d8 i/o bidirectional data bus . this bidirectional bus is used as the upper 8 bits of the data bus when in the 16-bit mode, and not used when in the 8-bit mode. (56-pin only) 43 ? d9 i/o 41 ? d10 i/o 40 ? d11 i/o 38 ? d12 i/o 36 ? d13 i/o 34 ? d14 i/o 33 ? d15 i/o 1 c1 clk output clock . this output is used for clocking the receive and transmit parallel data on the d[15:0] bus. 10 d5 reset input n/a active high reset . resets the entire chip. this pin is normally tied to v cc through a 0.1- f capacitor and to gnd through a 100k resistor for a 10 msec rc time constant. 19 e4 xcvrselect input n/a transceiver select . this signal selects between the full speed (fs) and the high speed (hs) transceivers: 0: hs transceiver enabled 1: fs transceiver enabled 20 e3 termselect input n/a termination select . this signal selects between the between the full speed (fs) and the high speed (hs) terminations: 0: hs termination 1: fs termination 9 e5 suspend input n/a suspend . places the cy7c68000 in a mode that draws minimal power from supplies. shuts down all blocks not necessary for suspend/resume opera- tions. while suspended, termselect must always be in fs mode to ensure that the 1.5 k ohm pull-up on dplus remains powered. 0: cy7c68000 circuitry drawing suspend current 1: cy7c68000 circuitry drawing normal current 26 g1 linestate1 output line state . these signals reflect the current state of the single-ended receivers. they are combinatorial until a ? usable ? clk is available then they are synchronized to clk. they directly reflect the current state of the dplus (linestate0) and dminus (linestate1). d- d+ description 0 0 0: se0 0 1 1: ? j ? state 1 0 2: ? k ? state 1 1 3: se1 table 5-1. pin descriptions (continued) [1] 56 48 name type default description
cy7c68000 document #: 38-08016 rev. *b page 8 of 14 25 h1 linestate0 output line state . these signals reflect the current state of the single-ended receivers. they are combinatorial until a ? usable ? clk is available then they are synchronized to clk. they directly reflect the current state of the dplus (linestate0) and dminus (linestate1). d- d+ description 00 ? 0: se0 01 ? 1: ? j ? state 10 ? 2: ? k ? state 11 ? 3: se1. 22 f1 opmode1 input operational mode . these signals select among various operational modes: 10 description 00 ? 0: normal operation 01 ? 1: non-driving 10 ? 2: disable bit stuffing and nrzi encoding 11 ? 3: reserved. 21 f3 opmode0 input operational mode. these signals select among various operational modes: 10 description 00 ? 0: normal operation 01 ? 1: non-driving 10 ? 2: disable bit stuffing and nrzi encoding 11 ? 3: reserved. 5 d6 txvalid input transmit valid . indicates that the data bus is valid. the assertion of transmit valid initiates sync on the usb. the negation of transmit valid initiates eop on the usb. the start of sync must be initiated on the usb no less than one or no more that two clks after the assertion of txvalid. in hs (xcvrselect = 0) mode, the sync pattern must be asserted on the usb between eight and 16 bit times after the assertion of txvalid is detected by the transmit state machine. in fs (xcvr = 1), the sync pattern must be asserted on the usb no less than one or more than two clks after the assertion of txvalid is detected by the transmit state machine. 8 e6 txready output transmit data ready . if txvalid is asserted, the sie must always have data available for clocking in to the tx holding register on the rising edge of clk. if txvalid is true and txready is asserted at the rising edge of clk, the cy7c68000 will load the data on the data bus into the tx holding register on the next rising edge of clk. at that time, the sie should immediately present the data for the next transfer on the data bus . 28 e1 rxvalid output receive data valid . indicates that the dataout bus has valid data. the receive data holding register is full and ready to be unloaded. the sie is expected to latch the dataout bus on the clock edge. 29 e2 rxactive output receive active . indicates that the receive state machine has detected sync and is active. rxactive is negated after a bit stuff error or an eop is detected. 30 h2 rxerror output receive error. 0 indicates no error. 1 indicates that a receive error has been detected. 7 ? validh i/o validh . this signal indicates that the high-order 8 bits of a 16-bit data word presented on the data bus are valid. when databus16_8 = 1 and txvalid = 0, validh is an output, indicating that the high-order receive data byte on the data bus is valid. when databus16_8 = 1 and txvalid = 1, validh is an input and indicates that the high-order transmit data byte, presented on the data bus by the transceiver, is valid. when databus16_8 = 0, validh is undefined. the status of the receive low-order data byte is determined by rxvalid and are present on d0 ? d7. table 5-1. pin descriptions (continued) [1] 56 48 name type default description
cy7c68000 document #: 38-08016 rev. *b page 9 of 14 2 ? databus16_8 input data bus 16_8 . selects between 8 and 16 bit data transfers. 1 ? 16-bit data path operation enabled. clk = 30 mhz. 0 ? 8-bit data path operation enabled. when uni_bidi = 0, d[8:15] are unde- fined. when uni_bidi =1, d[0:7] are valid on rxvalid and d[8:15] are valid on txvalid. clk = 60 mhz note that 16-bit operation is only an option for a hs/fs transceiver imple- mentation. [2] 13 a6 xtalin input n/a crystal input . connect this signal to a 24-mhz parallel-resonant, funda- mental mode crystal and 20-pf capacitor to gnd. it is also correct to drive xtalin with an external 24-mhz square wave de- rived from another clock source. 12 a5 xtalout output n/a crystal output . connect this signal to a 24-mhz parallel-resonant, funda- mental mode crystal and 30-pf (nominal) capacitor to gnd. if an external clock is used to drive xtalin, leave this pin open. 3 ? uni_bidi input driving this pin high enables the unidirectional mode when the eight-bit interface is selected. uni_bidi is static after power on reset (por). 6b5v cc power v cc . connect to 3.3v power source. 24 c3 v cc power n/a v cc . connect to 3.3v power source. 35 c4 v cc power n/a v cc . connect to 3.3v power source. 39 c5 v cc power n/a v cc . connect to 3.3v power source. 52 d3 v cc power n/a v cc . connect to 3.3v power source. 4 b2 gnd ground n/a ground. 23 b4 gnd ground n/a ground. 27 c2 gnd ground n/a ground. 37 d1 gnd ground n/a ground. 49 d2 gnd ground n/a ground. 31 g1 reserved input connect pin to ground. 54 f6 reserved input connect pin to ground. 47 f5 reserved input connect pin to ground. 42 f4 reserved input connect pin to ground. 32 f2 reserved input connect pin to ground. ? a4 reserved input connect pin to ground. ? b3 reserved input connect pin to ground. note: 2. databus16_8 is static after power-on reset (por) and is only sampled by the macrocell on the negation of reset. table 5-1. pin descriptions (continued) [1] 56 48 name type default description
cy7c68000 document #: 38-08016 rev. *b page 10 of 14 6.0 absolute maximum ratings storage temperature ............................................................ ............................................... .............................. ? 65 c to +150 c ambient temperature with power supplied ........................... ............................................................. ......................0 c to +70 c supply voltage to ground potential ....................................... ...................................................... .......................... ? 0.5v to +4.0v dc input voltage to any input pin ......................................... ..................................................... ....................................... 5.25 v dc voltage applied to outputs in high-z state ..................... ............................................................. .......... ? 0.5v to v cc + 0.5v power dissipation .................................................................. ............................................ ...............................................630 mw static discharge voltage ........................................................ ............................................... ........................................... > 2000v max output current, per io pin.............................................. ................................................... ........................................... 4 ma max output current, all 21 ? io pins (56-pin package) and 12 ? io pins (48-pin package) ............................................... 84/48 ma 7.0 operating conditions t a (ambient temperature under bias) .................................. ............................................................ .......................0 c to +70 c supply voltage ....................................................................... .......................................... ...................................... +3.0v to +3.6v ground voltage ...................................................................... ........................................... ........................................................ 0v f osc (oscillator or crystal frequency) .................................. ............................................................ ..............24 mhz 100 ppm ............................................................................................... parallel resonant 8.0 dc characteristics 8.1 usb 2.0 transceiver usb 2.0 certified in fs and hs modes. table 8-1. dc characteristics parameter description conditions min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v v ih input high voltage 2 5.25 v v il input low voltage ? 0.5 0.8 v i i input leakage current 0< v in < v cc 10 a v oh output voltage high i out = 4 ma 2.4 v v ol output low voltage i out = ? 4 ma 0.4 v i oh output current high 4ma i ol output current low 4ma c in input pin capacitance except dplus/dminus/clk 10 pf dplus/dminus/clk 15 pf c load maximum output capacitance output pins 30 pf i susp suspend current includes 1.5k ohm internal pull-up 235 270 a without 1.5k ohm internal pull-up 15 32 ua i cc supply current hs mode normal operation opmod[1:0] = 00 175 ma i cc supply current fs mode normal operation opmod[1:0] = 00 90 ma
cy7c68000 document #: 38-08016 rev. *b page 11 of 14 9.0 ac electrical characteristics 9.1 usb 2.0 transceiver usb 2.0 certified in fs and hs. 9.2 timing diagram 9.2.1 hs/fs interface timing?60 mhz 9.2.2 hs/fs interface timing?30 mhz table 9-1. 60-mhz interface timing constraints parameters parameter description min. typ. max. unit notes t csu_min minimum set-up time for txvalid 8 ns t ch_min minimum hold time for txvalid 1 ns t dsu_min minimum set-up time for data (transmit direction) 8 ns t dh_min minimum hold time for data (transmit direction) 1 ns t cco clock to control out time for txready, rxvalid, rxactive and rxerror 18ns t cdo clock to data out time (receive direction) 1 8 ns table 9-2. 30 mhz timing interface timing constraints parameters parameter description min. typ. max. unit notes t csu_min minimum set-up time for txvalid 20 ns t ch_min minimum hold time for txvalid 1 ns t dsu_min minimum set-up time for data (transmit direction) 20 ns t dh_min minimum hold time for data (transmit direction) 1 ns tcsu_min tch_min tdsu_min tdh_min tdco tcco datain dataout control_out control_in clk figure 9-1. 60-mhz interface timing constraints tcsu_min tch_min tdsu_min tdh_min tcvo tcco datain dataout control_out control_in clk tcdo tvsu_min tvh_min figure 9-2. 30-mhz timing interface timing constraints
cy7c68000 document #: 38-08016 rev. *b page 12 of 14 10.0 ordering information 11.0 package diagrams the tx2 is available in two packages: 56-pin ssop 48-pin fbga. t cco clock to control out time for txready, rxvalid, rxactive and rxerror 120ns t cdo clock to data out time (receive direction) 1 20 ns t vsu_min minimum set-up time for validh (transmit direction) 20 ns t vh_min minimum hold time for validh (transmit direction 1 ns t cvo clock to validh out time (receive direction) 1 20 ns table 10-1. ordering information ordering code package type CY7C68000-48BAC 48 fbga cy7c68000-56pvc 56 ssop cy7c68000-56pvct 56 ssop tape/reel table 9-2. 30 mhz timing interface timing constraints parameters (continued) 51-85062-*c figure 11-1. 56-lead shrunk small outline package o56 56- l ead shrunk small outline package o56
cy7c68000 document #: 38-08016 rev. *b page 13 of 14 ? cypress semiconductor corporation, 2002. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. ez-usb is a registered trademark and tx2 is a trademark of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their respective holders. figure 11-2. 48-pin fine pitch ball grid array (7 x 7 x 1.2 mm) ba48a 48-ball (7.00 mm x 7.00 mm x 1.2 mm) fbga ba48a 51-85096-*e
cy7c68000 document #: 38-08016 rev. *b page 14 of 14 document history page document title: cy7c68000 tx2 ? usb 2.0 utmi transceiver document number: 38-08016 rev. ecn no. issue date orig. of change description of change ** 112019 03/01/02 kku new data sheet *a 113885 07/01/02 kku updated pinouts on bga package, signal names. added timing diagrams. *b 118521 11/18/02 kku/ bha added usb logo. updated characterization data. changed from preliminary to final.

▲Up To Search▲

Price & Availability of CY7C68000-48BAC

	To Download CY7C68000-48BAC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .